MPLR2025 Talk

Co-operative JIT Compilation for Resource-Constrained Low-Power Coprocessors

Go Suzuki, Takuo Watanabe, Sosuke Moriguchi
22nd ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes (MPLR 2025), Singapore, Oct., 14, 2025. (to appear)

Abstract

As IoT devices evolve, their microcontroller systems-on-a-chip (SoCs) require higher performance, larger memory, and richer peripherals, resulting in increased power consumption. Integrating low-power (LP) coprocessors into SoCs offers a means to reduce power usage while preserving responsiveness, particularly in sensing tasks. However, LP coprocessors are constrained by limited memory and demand complex, platform-specific handling. These constraints often necessitate application refactoring and careful coordination of inter-processor communication.

We propose a JIT compilation design for managed languages to enhance the efficiency of LP coprocessor usage. These languages tend to increase code size due to dynamic dispatch and runtime checks. Our key idea is a cooperative approach: the interpreter on the main processor traces the application to compile only type-specialized basic blocks to be executed by the LP coprocessor. By combining trace-based compilation with lazy basic block versioning, the approach minimizes the code footprint and reduces processor interaction.

We implemented a prototype for a subset of the dynamically typed, object-oriented language mruby. The prototype supports runtime type checking even on LP coprocessors. This paper presents its design and implementation, along with evaluations on selected applications using LP coprocessors. We report power consumption and code size measurements obtained on the ESP32-C6.